The present invention relates to computer architectures and in particular to a computer architecture that employs multiple interconnected tiles each providing a range of alternative computational or memory storage capabilities.
Common computer architectures employ intercommunication computational structures (e.g., processors) and storage structures (e.g., memory) that are highly compartmentalized. This compartmentalization permits the modularity of the hardware design, i.e., circuitry of each of the structures to be designed in different methodologies and manufactured in different types of foundries from different industries.
The drawback to this specialization and compartmentalization is the creation of data access bottlenecks between computational structures and storage structures that can greatly slow computation and waste of energy in transporting data between different structure locations.
For this reason, it is generally known to distribute memory elements among computational elements. For example, cache structures may be used in which small local memories are closely associated with each processor. These small local memories are preloaded with data that is expected to be used during processing to avoid the delays of obtaining the same data from a larger, more remote structure. Alternatively or in addition, distributed memory models may be used where each of multiple processors is associated with a different block of a main memory. This approach provides multiple paths between memory and processors avoiding the bottleneck of a single data channel for a very large memory.
Each of these techniques necessarily must anticipate the amount of memory that will be needed by a given process in making a distribution of the memory structures. To the extent that those assumptions about memory use are inaccurate or vary, after the distribution, wasteful excess memory can be allocated or time-consuming memory transfers from other locations can be required.